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FCCM
2006
IEEE
133views VLSI» more  FCCM 2006»
15 years 9 months ago
A Scalable FPGA-based Multiprocessor
It has been shown that a small number of FPGAs can significantly accelerate certain computing tasks by up to two or three orders of magnitude. However, particularly intensive lar...
Arun Patel, Christopher A. Madill, Manuel Salda&nt...
EGH
2004
Springer
15 years 8 months ago
Realtime ray tracing of dynamic scenes on an FPGA chip
Realtime ray tracing has recently established itself as a possible alternative to the current rasterization approach for interactive 3D graphics. However, the performance of exist...
Jörg Schmittler, Sven Woop, Daniel Wagner, Wo...
136
Voted
ICS
2003
Tsinghua U.
15 years 8 months ago
AEGIS: architecture for tamper-evident and tamper-resistant processing
We describe the architecture for a single-chip aegis processor which can be used to build computing systems secure against both physical and software attacks. Our architecture ass...
G. Edward Suh, Dwaine E. Clarke, Blaise Gassend, M...
166
Voted
ASAP
2002
IEEE
170views Hardware» more  ASAP 2002»
15 years 8 months ago
Reviewing 4-to-2 Adders for Multi-Operand Addition
Recently there has been quite a number of papers discussing the use of redundant 4-to-2 adders for the accumulation of partial products in multipliers, claiming one type to be sup...
Peter Kornerup
FCCM
2002
IEEE
126views VLSI» more  FCCM 2002»
15 years 8 months ago
Hyperspectral Image Compression on Reconfigurable Platforms
NASA’s satellites currently do not make use of advanced image compression techniques during data transmission to earth because of limitations in the available platforms. With th...
Thomas W. Fry, Scott Hauck