5553 search results - page 226 / 1111 » Parallel Implementation of Sch |
127
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FCCM
2009
IEEE
15 years 10 months ago
2009
IEEE
The Ambric Massively Parallel Processor Array (MPPA) is a device that contains 336 32-bit RISC processors and is appropriate for embedded systems due to its relatively small physi...
93
Voted
EUROPAR
2007
Springer
15 years 10 months ago
2007
Springer
STL dictionaries like map and set are commonly used in C++ programs. We consider parallelizing two of their bulk operations, namely the construction from many elements, and the ins...
121
Voted
ROBIO
2006
IEEE
15 years 10 months ago
2006
IEEE
— The architecture optimization of a three degrees of freedom (3-DOF) planar cable-driven parallel manipulator (CDPM) with multiple objectives has been implemented by means of GA...
134
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SIPS
2006
IEEE
15 years 10 months ago
2006
IEEE
Abstract— In this paper, we propose partly parallel architectures based on optimal overlapped sum-product (OSP) decoding. To ensure high throughput and hardware utilization effi...
116
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CAMP
2005
IEEE
15 years 9 months ago
2005
IEEE
— In this paper, we propose a new architecture that can extract information of numerous objects in an image at highspeed. Various characteristics can be obtained from the image m...