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SI3D
2006
ACM
16 years 8 days ago
Hardware accelerated multi-resolution geometry synthesis
In this paper, we propose a new technique for hardware accelerated multi-resolution geometry synthesis. The level of detail for a given viewpoint is created on-the-fly, allowing f...
Martin Bokeloh, Michael Wand
SC
2004
ACM
15 years 11 months ago
Performance Evaluation of Task Pools Based on Hardware Synchronization
A task-based execution provides a universal approach to dynamic load balancing for irregular applications. Tasks are arbitrary units of work that are created dynamically at runtim...
Ralf Hoffmann, Matthias Korch, Thomas Rauber
CLUSTER
2003
IEEE
15 years 11 months ago
Application-Bypass Reduction for Large-Scale Clusters
Process skew is an important factor in the performance of parallel applications, especially in large-scale clusters. Reduction is a common collective operation which, by its natur...
Adam Wagner, Darius Buntinas, Dhabaleswar K. Panda...
ISORC
1998
IEEE
15 years 10 months ago
The Time-Triggered Architecture
The Time-Triggered Architecture (TTA) provides a computing infrastructure for the design and implementation of dependable distributed embedded systems. A large real-time applicatio...
Hermann Kopetz
SPAA
1990
ACM
15 years 10 months ago
Wait-Free Data Structures in the Asynchronous PRAM Model
A wad-free implementation of a data object in shared memory is one that guarantees that any process can complete any operation in a finite number of steps, regardless of the execu...
James Aspnes, Maurice Herlihy