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ISCA
2008
IEEE
113views Hardware» more  ISCA 2008»
15 years 11 months ago
A Two-Level Load/Store Queue Based on Execution Locality
Multicore processors have emerged as a powerful platform on which to efficiently exploit thread-level parallelism (TLP). However, due to Amdahl’s Law, such designs will be incr...
Miquel Pericàs, Adrián Cristal, Fran...
MICRO
2008
IEEE
118views Hardware» more  MICRO 2008»
15 years 11 months ago
Notary: Hardware techniques to enhance signatures
Hardware signatures have been recently proposed as an efficient mechanism to detect conflicts amongst concurrently running transactions in transactional memory systems (e.g., Bulk...
Luke Yen, Stark C. Draper, Mark D. Hill
AINA
2007
IEEE
15 years 10 months ago
Database-Driven Grid Computing with GridBASE
The GridBASE framework for database-driven grid computing is presented. The design and a prototype implementation of the framework is discussed. Industry-strength database technol...
Hans De Sterck, Chen Zhang, Aleks Papo
COLCOM
2007
IEEE
15 years 10 months ago
Peer2Schedule - an experimental peer-to-peer application to support present collaboration
Abstract—This paper describes experiences from implementing an experimental mobile peer-to-peer application called Peer2Schedule aimed at improving and supporting collaboration w...
Alf Inge Wang, Peter Nicolai Motzfeldt
DDECS
2007
IEEE
175views Hardware» more  DDECS 2007»
15 years 10 months ago
Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair
—An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. A commonly used repair strategy is to equip memories with sp...
Philipp Öhler, Sybille Hellebrand, Hans-Joach...