88 search results - page 10 / 18 » Parallel Logic Simulation of VLSI Systems |
162
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FCCM
1997
IEEE
15 years 9 months ago
1997
IEEE
We propose an FPGA chip architecture based on a conventional FPGA logic array core, in which I/O pins are clocked at a much higher rate than that of the logic array that they serv...
150
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ISCAS
2006
IEEE
15 years 11 months ago
2006
IEEE
A robust system architecture to achieve optical coherency free optimization. Several methods that had been proposed in the in multiple-beam free-space laser communication links wit...
119
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DFT
2007
IEEE
15 years 11 months ago
2007
IEEE
Decreasing feature sizes have led to an increased vulnerability of random logic to soft errors. A particle strike may cause a glitch or single event transient (SET) at the output ...
139
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IPPS
2003
IEEE
15 years 10 months ago
2003
IEEE
This paper investigates a complexity-effective technique for verifying a highly distributed directory-based cache coherence protocol. We develop a novel approach called “witnes...
160
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CAV
2005
Springer
15 years 10 months ago
2005
Springer
Statistical methods to model check stochastic systems have been, thus far, developed only for a sublogic of continuous stochastic logic (CSL) that does not have steady state operat...