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IJPP
2011
99views more  IJPP 2011»
14 years 4 months ago
Regular Lattice and Small-World Spin Model Simulations Using CUDA and GPUs
Data-parallel accelerator devices such as Graphical Processing Units (GPUs) are providing dramatic performance improvements over even multicore CPUs for lattice-oriented applicatio...
Kenneth A. Hawick, Arno Leist, Daniel P. Playne
88
Voted
SAFECOMP
2010
Springer
14 years 8 months ago
Reliability Analysis of Safety-Related Communication Architectures
Abstract. In this paper we describe a novel concept for reliability analysis of communication architectures in safety-critical systems. This concept has been motivated by applicati...
Oliver Schulz, Jan Peleska
ISCA
2011
IEEE
287views Hardware» more  ISCA 2011»
14 years 1 months ago
Scalable power control for many-core architectures running multi-threaded applications
Optimizing the performance of a multi-core microprocessor within a power budget has recently received a lot of attention. However, most existing solutions are centralized and cann...
Kai Ma, Xue Li, Ming Chen, Xiaorui Wang
JTRES
2010
ACM
14 years 10 months ago
The embedded Java benchmark suite JemBench
Requirements to embedded systems increase steadily. In parallel, also the performance of the processors used in these systems is improved leading to multithreaded and/or multicore...
Martin Schoeberl, Thomas B. Preußer, Sascha ...
71
Voted
IPPS
2010
IEEE
14 years 7 months ago
User level DB: a debugging API for user-level thread libraries
With the advent of the multicore era, parallel programming is becoming ubiquitous. Multithreading is a common approach to benefit from these architectures. Hybrid M:N libraries lik...
Kevin Pouget, Marc Pérache, Patrick Carriba...