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FPL
2006
Springer
105views Hardware» more  FPL 2006»
15 years 1 months ago
A Scalable Network ASIP Enabling Flow Awareness in Ethernet Access
In this paper we research an FPGA based Application Specific Instruction Set Processor (ASIP) tailored to the needs of a flow aware Ethernet access node. The processor has an arch...
K. Van Renterghem, Dieter Verhulst, S. Verschuere,...
IPPS
2010
IEEE
14 years 7 months ago
Offline library adaptation using automatically generated heuristics
Automatic tuning has emerged as a solution to provide high-performance libraries for fast changing, increasingly complex computer architectures. We distinguish offline adaptation (...
Frédéric de Mesmay, Yevgen Voronenko...
ITNG
2010
IEEE
14 years 8 months ago
Record Setting Software Implementation of DES Using CUDA
—The increase in computational power of off-the-shelf hardware offers more and more advantageous tradeoffs among efficiency, cost and availability, thus enhancing the feasibil...
Giovanni Agosta, Alessandro Barenghi, Fabrizio De ...
TCS
2011
14 years 4 months ago
Highly concurrent multi-word synchronization
d Abstract) Hagit Attiya and Eshcar Hillel Department of Computer Science, Technion The design of concurrent data structures is greatly facilitated by the availability of synchroni...
Hagit Attiya, Eshcar Hillel
72
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IPPS
2009
IEEE
15 years 4 months ago
A metascalable computing framework for large spatiotemporal-scale atomistic simulations
A metascalable (or “design once, scale on new architectures”) parallel computing framework has been developed for large spatiotemporal-scale atomistic simulations of materials...
Ken-ichi Nomura, Richard Seymour, Weiqiang Wang, H...