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IEEEPACT
2005
IEEE
15 years 3 months ago
Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window
Current integration trends embrace the prosperity of single-chip multi-core processors. Although multi-core processors deliver significantly improved system throughput, single-thr...
Huiyang Zhou
JSA
2010
173views more  JSA 2010»
14 years 4 months ago
Hardware/software support for adaptive work-stealing in on-chip multiprocessor
During the past few years, embedded digital systems have been requested to provide a huge amount of processing power and functionality. A very likely foreseeable step to pursue th...
Quentin L. Meunier, Frédéric P&eacut...
HIPC
2007
Springer
15 years 3 months ago
Optimization of Collective Communication in Intra-cell MPI
: The Cell is a heterogeneous multi-core processor, which has eight co-processors, called SPEs. The SPEs can access a common shared main memory through DMA, and each SPE can direct...
M. K. Velamati, Arun Kumar, Naresh Jayam, Ganapath...
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WWW
2010
ACM
15 years 4 months ago
Fast and parallel webpage layout
The web browser is a CPU-intensive program. Especially on mobile devices, webpages load too slowly, expending significant time in processing a document’s appearance. Due to powe...
Leo A. Meyerovich, Rastislav Bodík
EDBT
2010
ACM
155views Database» more  EDBT 2010»
15 years 29 days ago
Suffix tree construction algorithms on modern hardware
Suffix trees are indexing structures that enhance the performance of numerous string processing algorithms. In this paper, we propose cache-conscious suffix tree construction algo...
Dimitris Tsirogiannis, Nick Koudas