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» Parallel Memory Architecture for Arbitrary Stride Accesses
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108
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EUROPAR
1997
Springer
15 years 4 months ago
Prefetching and Multithreading Performance in Bus-Based Multiprocessors with Petri Nets
The large latency of memory accesses is a major obstacle in obtaining high processor utilization in large scale shared-memory multiprocessors. Access to remote memory is likely to ...
Edward D. Moreno, Sergio Takeo Kofuji, Marcelo H. ...
MICRO
2000
IEEE
176views Hardware» more  MICRO 2000»
15 years 10 days ago
An Advanced Optimizer for the IA-64 Architecture
level of abstraction, compared with the program representation for scalar optimizations. For example, loop unrolling and loop unrolland-jam transformations exploit the large regist...
Rakesh Krishnaiyer, Dattatraya Kulkarni, Daniel M....
FPGA
2010
ACM
181views FPGA» more  FPGA 2010»
15 years 3 months ago
Efficient multi-ported memories for FPGAs
Multi-ported memories are challenging to implement with FPGAs since the provided block RAMs typically have only two ports. We present a thorough exploration of the design space of...
Charles Eric LaForest, J. Gregory Steffan
116
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PVM
2010
Springer
14 years 11 months ago
Adaptive MPI Multirail Tuning for Non-uniform Input/Output Access
Multicore processors have not only reintroduced Non-Uniform Memory Access (NUMA) architectures in nowadays parallel computers, but they are also responsible for non-uniform access ...
Stephanie Moreaud, Brice Goglin, Raymond Namyst
IPPS
1992
IEEE
15 years 4 months ago
CCHIME: A Cache Coherent Hybrid Interconnected Memory Extension
This paper presents a hybrid shared memory architecture which combines the scalability of a multistage interconnection network with the contention reduction benefits of coherent c...
Matthew K. Farrens, Arvin Park, Allison Woodruff