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» Parallel Memory Architecture for Arbitrary Stride Accesses
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CORR
2011
Springer
177views Education» more  CORR 2011»
14 years 4 months ago
Measuring NUMA effects with the STREAM benchmark
Modern high-end machines feature multiple processor packages, each of which contains multiple independent cores and integrated memory controllers connected directly to dedicated ph...
Lars Bergstrom
ICPP
1998
IEEE
15 years 1 months ago
A memory-layout oriented run-time technique for locality optimization
Exploiting locality at run-time is a complementary approach to a compiler approach for those applications with dynamic memory access patterns. This paper proposes a memory-layout ...
Yong Yan, Xiaodong Zhang, Zhao Zhang
SOFTVIS
2003
ACM
15 years 2 months ago
Interactive Locality Optimization on NUMA Architectures
Optimizing the performance of shared-memory NUMA programs remains something of a black art, requiring that application writers possess deep understanding of their programs’ beha...
Tao Mu, Jie Tao, Martin Schulz, Sally A. McKee
LCPC
2007
Springer
15 years 3 months ago
Revisiting SIMD Programming
Massively parallel SIMD array architectures are making their way into embedded processors. In these architectures, a number of identical processing elements having small private st...
Anton Lokhmotov, Benedict R. Gaster, Alan Mycroft,...
HPCA
2006
IEEE
15 years 10 months ago
InfoShield: a security architecture for protecting information usage in memory
Cyber theft is a serious threat to Internet security. It is one of the major security concerns by both network service providers and Internet users. Though sensitive information c...
Guofei Gu, Hsien-Hsin S. Lee, Joshua B. Fryman, Ju...