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123
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MICRO
2010
IEEE
153views Hardware» more  MICRO 2010»
15 years 16 days ago
Throughput-Effective On-Chip Networks for Manycore Accelerators
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
Ali Bakhoda, John Kim, Tor M. Aamodt
123
Voted
HIPC
2009
Springer
15 years 12 days ago
Detailed analysis of I/O traces for large scale applications
- In this paper, we present a tool to extract I/O traces from very large applications running at full scale during their production runs. We analyze these traces to gain informatio...
Nithin Nakka, Alok N. Choudhary, Wei-keng Liao, Le...
158
Voted
HOTI
2011
IEEE
14 years 2 months ago
iWISE: Inter-router Wireless Scalable Express Channels for Network-on-Chips (NoCs) Architecture
Abstract—Network-on-Chips (NoCs) paradigm is fast becoming a defacto standard for designing communication infrastructure for multicores with the dual goals of reducing power cons...
Dominic DiTomaso, Avinash Kodi, Savas Kaya, David ...
96
Voted
HPDC
2010
IEEE
15 years 3 months ago
Exploring the RNA folding energy landscape using scalable distributed cyberinfrastructure
The increasing significance of RNAs in transcriptional or post-transcriptional gene regulation processes has generated considerable interest towards the prediction of RNA folding ...
Joohyun Kim, Wei Huang, Sharath Maddineni, Fareed ...
126
Voted
IPMI
2009
Springer
16 years 3 months ago
Oriented Morphometry of Folds on Surfaces
Abstract. The exterior surface of the brain is characterized by a juxtaposition of crests and troughs that together form a folding pattern. The majority of the deformations that oc...
Maxime Boucher, Alan C. Evans, Kaleem Siddiqi