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172
Voted
ISCA
2006
IEEE
187views Hardware» more  ISCA 2006»
15 years 9 months ago
A Case for MLP-Aware Cache Replacement
Performance loss due to long-latency memory accesses can be reduced by servicing multiple memory accesses concurrently. The notion of generating and servicing long-latency cache m...
Moinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu,...
157
Voted
HPDC
2005
IEEE
15 years 9 months ago
Genetic algorithm based automatic data partitioning scheme for HPF
good data partitioning scheme is the need of the time. However it is very diflcult to arrive at a good solution as the number of possible dutupartitionsfor a given real lifeprogra...
Sunil Kumar Anand, Y. N. Srikant
136
Voted
ICS
2004
Tsinghua U.
15 years 9 months ago
Evaluating support for global address space languages on the Cray X1
The Cray X1 was recently introduced as the first in a new line of parallel systems to combine high-bandwidth vector processing with an MPP system architecture. Alongside capabili...
Christian Bell, Wei-Yu Chen, Dan Bonachea, Katheri...
133
Voted
IPPS
2003
IEEE
15 years 9 months ago
Extending OpenMP to Support Slipstream Execution Mode
OpenMP has emerged as a widely accepted standard for writing shared memory programs. Hardware-specific extensions such as data placement are usually needed to improve the scalabi...
Khaled Z. Ibrahim, Gregory T. Byrd
166
Voted
IPPS
2003
IEEE
15 years 9 months ago
Distributed P2P Computing within Triana: A Galaxy Visualization Test Case
We discuss here a parallel implementation of the visualisation of data from a galaxy formation simulation within the Triana problem-solving environment. The visualisation is a tes...
Ian J. Taylor, Matthew S. Shields, Ian Wang, Roger...