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» Parallel Mesh Refinement Without Communication
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ICPP
2005
IEEE
15 years 3 months ago
Peak Power Control for a QoS Capable On-Chip Network
In recent years integrating multiprocessors in a single chip is emerging for supporting various scientific and commercial applications, with diverse demands to the underlying on-c...
Yuho Jin, Eun Jung Kim, Ki Hwan Yum
HPCA
1996
IEEE
15 years 1 months ago
Fault-Tolerance with Multimodule Routers
The current multiprocessors such asCray T3D support interprocessor communication using partitioned dimension-order routers (PDRs). In a PDR implementation, the routing logic and sw...
Suresh Chalasani, Rajendra V. Boppana
PODC
2005
ACM
15 years 3 months ago
Routing complexity of faulty networks
One of the fundamental problems in distributed computing is how to efficiently perform routing in a faulty network in which each link fails with some probability. This paper inves...
Omer Angel, Itai Benjamini, Eran Ofek, Udi Wieder
85
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DCOSS
2006
Springer
15 years 1 months ago
Efficient In-Network Processing Through Local Ad-Hoc Information Coalescence
We consider in-network processing via local message passing. The considered setting involves a set of sensors each of which can communicate with a subset of other sensors. There is...
Onur Savas, Murat Alanyali, Venkatesh Saligrama
HPCA
2009
IEEE
15 years 10 months ago
Prediction router: Yet another low latency on-chip router architecture
Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core architectures. To reduce th...
Hiroki Matsutani, Michihiro Koibuchi, Hideharu Ama...