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EUROPAR
2000
Springer
15 years 1 months ago
Cache Remapping to Improve the Performance of Tiled Algorithms
With the increasing processing power, the latency of the memory hierarchy becomes the stumbling block of many modern computer architectures. In order to speed-up the calculations, ...
Kristof Beyls, Erik H. D'Hollander
SPDP
1991
IEEE
15 years 1 months ago
Local vs. global memory in the IBM RP3: experiments and performance modelling
A number of experiments regarding the placement of instructions, private data and shared data in the Non-Uniform-Memory-Access multiprocessor, RP3 has been performed. Three Scient...
Mats Brorsson
HPCA
2007
IEEE
15 years 10 months ago
Implications of Device Timing Variability on Full Chip Timing
As process technologies continue to scale, the magnitude of within-die device parameter variations is expected to increase and may lead to significant timing variability. This pap...
Murali Annavaram, Ed Grochowski, Paul Reed
EDOC
2003
IEEE
15 years 3 months ago
Towards a Language for Coherent Enterprise Architecture Descriptions
A coherent description of architectures provides insight, enables communication among different stakeholders and guides complicated (business and ICT) change processes. Unfortunat...
Henk Jonkers, René van Buuren, Farhad Arbab...
HPCA
2009
IEEE
15 years 10 months ago
Prediction router: Yet another low latency on-chip router architecture
Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core architectures. To reduce th...
Hiroki Matsutani, Michihiro Koibuchi, Hideharu Ama...