Sciweavers

3660 search results - page 564 / 732
» Parallel Program Archetypes
Sort
View
ICS
1993
Tsinghua U.
15 years 10 months ago
Anatomy of a Message in the Alewife Multiprocessor
Shared-memory provides a uniform and attractive mechanism for communication. For efficiency, it is often implemented with a layer of interpretive hardware on top of a message-pas...
John Kubiatowicz, Anant Agarwal
HPCN
1994
Springer
15 years 10 months ago
Three-Dimensional Simulation of Semiconductor Devices
The exact knowledge of the heat flow in heterojunction bipolar transistors (HBT) during power operation is an important key factor for the systematic improvement of power density,...
Wilfried Klix, Ralf Dittmann, Roland Stenzel
ASPDAC
2007
ACM
119views Hardware» more  ASPDAC 2007»
15 years 10 months ago
Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space
Parallel prefix adder is the most flexible and widely-used binary adder for ASIC designs. Many high-level synthesis techniques have been developed to find optimal prefix structures...
Jianhua Liu, Yi Zhu, Haikun Zhu, Chung-Kuan Cheng,...
CASES
2007
ACM
15 years 10 months ago
Application driven embedded system design: a face recognition case study
The key to increasing performance without a commensurate increase in power consumption in modern processors lies in increasing both parallelism and core specialization. Core speci...
Karthik Ramani, Al Davis
DEBS
2007
ACM
15 years 10 months ago
A QoS policy configuration modeling language for publish/subscribe middleware platforms
Publish/subscribe (pub/sub) middleware platforms for eventbased distributed systems often provide many configurable policies that affect end-to-end quality of service (QoS). Altho...
Joe Hoffert, Douglas C. Schmidt, Aniruddha S. Gokh...