3660 search results - page 622 / 732 » Parallel Program Archetypes |
140
Voted
IPPS
2005
IEEE
15 years 10 months ago
2005
IEEE
The Distributed Shared Memory (DSM) model is designed to leverage the ease of programming of the shared memory paradigm, while enabling the highperformance by expressing locality ...
154
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ISCA
2005
IEEE
15 years 10 months ago
2005
IEEE
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...
156
Voted
ICS
2005
Tsinghua U.
15 years 10 months ago
2005
Tsinghua U.
Excessive power consumption is becoming a major barrier to extracting the maximum performance from high-performance parallel systems. Therefore, techniques oriented towards reduci...
160
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COORDINATION
2004
Springer
15 years 10 months ago
2004
Springer
The increasing ubiquity of mobile devices has led to an explosion in the development of applications tailored to the particular needs of individual users. As the research communit...
148
Voted
FPGA
2004
ACM
15 years 10 months ago
2004
ACM
The speedup over a microprocessor that can be achieved by implementing some programs on an FPGA has been extensively reported. This paper presents an analysis, both quantitative a...