3660 search results - page 710 / 732 » Parallel Program Archetypes |
MICRO
2010
IEEE
14 years 8 months ago
2010
IEEE
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
96
Voted
LCTRTS
2010
Springer
14 years 7 months ago
2010
Springer
Concurrent Action-Oriented Specifications (CAOS) model the behavior of a synchronous hardware circuit as asynchronous guarded at an abstraction level higher than the Register Tran...
102
click to vote
JSA
2010
14 years 4 months ago
2010
During the past few years, embedded digital systems have been requested to provide a huge amount of processing power and functionality. A very likely foreseeable step to pursue th...
107
click to vote
ISCA
2011
IEEE
14 years 1 months ago
2011
IEEE
A growing body of work has compiled a strong case for the single-ISA heterogeneous multi-core paradigm. A single-ISA heterogeneous multi-core provides multiple, differently-design...
124
click to vote
ICLP
2011
Springer
14 years 1 months ago
2011
Springer
Transaction Logic is an extension of classical logic that gracefully integrates both declarative and procedural knowledge and has proved itself as a powerful formalism for many ad...