1075 search results - page 118 / 215 » Parallel Programming with Transactional Memory |
157
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EUROPAR
2010
Springer
15 years 5 months ago
2010
Springer
Abstract. This paper is motivated by the desire to provide an efficient and scalable software cache implementation of OpenMP on multicore and manycore architectures in general, and...
131
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MICRO
2008
IEEE
15 years 11 months ago
2008
IEEE
Hardware signatures have been recently proposed as an efficient mechanism to detect conflicts amongst concurrently running transactions in transactional memory systems (e.g., Bulk...
134
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ICDCSW
2003
IEEE
15 years 10 months ago
2003
IEEE
Broadcasting provides an e cient means for disseminating information in both wired and wireless setting. In this paper, we study di erent client side cache organizations for vario...
163
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IEEEPACT
1998
IEEE
15 years 9 months ago
1998
IEEE
Software fine-grain distributed shared memory (FGDSM) provides a simplified shared-memory programming interface with minimal or no hardware support. Originally software FGDSMs tar...
140
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ICS
2009
Tsinghua U.
15 years 11 months ago
2009
Tsinghua U.
The Cell BE is a multicore processor with eight vector accelerators (called SPEs) that implement explicit cache management through direct memory access engines. While the Cell has...