1075 search results - page 120 / 215 » Parallel Programming with Transactional Memory |
125
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ICPP
2003
IEEE
15 years 8 months ago
2003
IEEE
Hardware prefetching is a simple and effective technique for hiding cache miss latency and thus improving the overall performance. However, it comes with addition of prefetch buff...
96
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ICS
2009
Tsinghua U.
15 years 7 months ago
2009
Tsinghua U.
Single-particle 3D reconstruction from cryo-electron microscopy (cryo-EM) images is a kernel application of biological molecules analysis, as the computational requirement of whic...
78
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ISCA
1997
IEEE
15 years 6 months ago
1997
IEEE
DataScalar architectures improve memory system performance by running computation redundantly across multiple processors, which are each tightly coupled with an associated memory....
112
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CISIS
2010
IEEE
15 years 9 months ago
2010
IEEE
—Current trends in desktop processor design have been toward many-core solutions with increased parallelism. As the number of supported threads grows in these processors, it may ...
124
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HPCA
2009
IEEE
16 years 3 months ago
2009
IEEE
Heterogeneous multicores, such as Cell BE processors and GPGPUs, typically do not have caches for their accelerator cores because coherence traffic, cache misses, and latencies fr...