Sciweavers

1075 search results - page 121 / 215
» Parallel Programming with Transactional Memory
Sort
View
143
Voted
FCCM
2002
IEEE
171views VLSI» more  FCCM 2002»
15 years 7 months ago
Coarse-Grain Pipelining on Multiple FPGA Architectures
Reconfigurable systems, and in particular, FPGA-based custom computing machines, offer a unique opportunity to define application-specific architectures. These architectures offer...
Heidi E. Ziegler, Byoungro So, Mary W. Hall, Pedro...
147
Voted
PLDI
2012
ACM
13 years 5 months ago
Speculative separation for privatization and reductions
Automatic parallelization is a promising strategy to improve application performance in the multicore era. However, common programming practices such as the reuse of data structur...
Nick P. Johnson, Hanjun Kim, Prakash Prabhu, Ayal ...
IPPS
2002
IEEE
15 years 7 months ago
Characterizing NAS Benchmark Performance on Shared Heterogeneous Networks
The goal of this research is to develop performance profiles of parallel and distributed applications in order to predict their execution time under different network conditions....
Jaspal Subhlok, Shreenivasa Venkataramaiah, Amitoj...
136
Voted
TPDS
2008
113views more  TPDS 2008»
15 years 2 months ago
Evaluating a High-Level Parallel Language (GpH) for Computational GRIDs
Computational Grids potentially offer low cost, readily available, and large-scale high-performance platforms. For the parallel execution of programs, however, computational GRIDs ...
Abdallah Al Zain, Philip W. Trinder, Greg Michaels...
96
Voted
TACAS
2010
Springer
142views Algorithms» more  TACAS 2010»
15 years 9 months ago
Tracking Heaps That Hop with Heap-Hop
Abstract. Heap-Hop is a program prover for concurrent heap-manipulating programs that use Hoare monitors and message-passing synchronization. Programs are annotated with pre and po...
Jules Villard, Étienne Lozes, Cristiano Cal...