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» Parallel Programming with Transactional Memory
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IPPS
1994
IEEE
15 years 8 months ago
Parallel Evaluation of a Parallel Architecture by Means of Calibrated Emulation
A parallel transputer-based emulator has been developed to evaluate the DDM--ahighlyparallel virtual shared memory architecture. The emulator provides performance results of a har...
Henk L. Muller, Paul W. A. Stallard, David H. D. W...
241
Voted
ASPLOS
2009
ACM
16 years 5 months ago
DMP: deterministic shared memory multiprocessing
Current shared memory multicore and multiprocessor systems are nondeterministic. Each time these systems execute a multithreaded application, even if supplied with the same input,...
Joseph Devietti, Brandon Lucia, Luis Ceze, Mark Os...
ICPP
2008
IEEE
15 years 11 months ago
Memory Access Scheduling Schemes for Systems with Multi-Core Processors
On systems with multi-core processors, the memory access scheduling scheme plays an important role not only in utilizing the limited memory bandwidth but also in balancing the pro...
Hongzhong Zheng, Jiang Lin, Zhao Zhang, Zhichun Zh...
FPGA
2007
ACM
124views FPGA» more  FPGA 2007»
15 years 11 months ago
A practical FPGA-based framework for novel CMP research
Chip-multiprocessors are quickly gaining momentum in all segments of computing. However, the practical success of CMPs strongly depends on addressing the difficulty of multithread...
Sewook Wee, Jared Casper, Njuguna Njoroge, Yuriy T...
CCGRID
2005
IEEE
15 years 10 months ago
View-oriented update protocol with integrated diff for view-based consistency
This paper proposes a View-Oriented Update Protocol with Integrated Diff for efficient implementation of a View-based Consistency model which supports a novel View-Oriented Paral...
Zhiyi Huang, Martin K. Purvis, Paul Werstein