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» Parallel Programming with Transactional Memory
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131
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SPAA
2003
ACM
15 years 10 months ago
Quantifying instruction criticality for shared memory multiprocessors
Recent research on processor microarchitecture suggests using instruction criticality as a metric to guide hardware control policies. Fields et al. [3, 4] have proposed a directed...
Tong Li, Alvin R. Lebeck, Daniel J. Sorin
150
Voted
HICSS
1995
IEEE
128views Biometrics» more  HICSS 1995»
15 years 8 months ago
Instruction Level Parallelism
Abstract. We reexamine the limits of parallelism available in programs, using runtime reconstruction of program data-flow graphs. While limits of parallelism have been examined in...
ICPP
2008
IEEE
15 years 11 months ago
Scalable Dynamic Load Balancing Using UPC
An asynchronous work-stealing implementation of dynamic load balance is implemented using Unified Parallel C (UPC) and evaluated using the Unbalanced Tree Search (UTS) benchmark ...
Stephen Olivier, Jan Prins
SIAMCOMP
1998
117views more  SIAMCOMP 1998»
15 years 4 months ago
The Queue-Read Queue-Write PRAM Model: Accounting for Contention in Parallel Algorithms
This paper introduces the queue-read, queue-write (qrqw) parallel random access machine (pram) model, which permits concurrent reading and writing to shared memory locations, but ...
Phillip B. Gibbons, Yossi Matias, Vijaya Ramachand...
CLUSTER
2000
IEEE
15 years 9 months ago
SilkRoad: A Multithreaded Runtime System with Software Distributed Shared Memory for SMP Clusters
Multithreaded parallel system with software Distributed Shared Memory (DSM) is an attractive direction in cluster computing. In these systems, distributing workloads and keeping t...
Liang Peng, Weng-Fai Wong, Ming-Dong Feng, Chung-K...