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ISPA
2004
Springer
15 years 8 months ago
A Fault Tolerance Protocol for Uploads: Design and Evaluation
This paper investigates fault tolerance issues in Bistro, a wide area upload architecture. In Bistro, clients first upload their data to intermediaries, known as bistros. A destin...
Leslie Cheung, Cheng-Fu Chou, Leana Golubchik, Yan...
128
Voted
MIDDLEWARE
2004
Springer
15 years 8 months ago
NeCoMan: middleware for safe distributed service deployment in programmable networks
Recent evolution in computer networks clearly demonstrates a trend towards complex and dynamic networks. To fully exploit the potential of such heterogeneous and rapidly evolving ...
Nico Janssens, Lieven Desmet, Sam Michiels, Pierre...
98
Voted
MIDDLEWARE
2004
Springer
15 years 8 months ago
Data pipelines: enabling large scale multi-protocol data transfers
Collaborating users need to move terabytes of data among their sites, often involving multiple protocols. This process is very fragile and involves considerable human involvement ...
Tevfik Kosar, George Kola, Miron Livny
130
Voted
CLUSTER
2003
IEEE
15 years 8 months ago
Implications of a PIM Architectural Model for MPI
Memory may be the only system component that is more commoditized than a microprocessor. To simultaneously exploit this and address the impending memory wall, processing in memory...
Arun Rodrigues, Richard C. Murphy, Peter M. Kogge,...
GLVLSI
2003
IEEE
173views VLSI» more  GLVLSI 2003»
15 years 8 months ago
40 MHz 0.25 um CMOS embedded 1T bit-line decoupled DRAM FIFO for mixed-signal applications
An embedded 40 MHz FIFO buffer for use in mixed-signal information processing applications is presented. The buffer design uses a 1T DRAM topology for its unit memory cell compone...
Michael I. Fuller, James P. Mabry, John A. Hossack...
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