Sciweavers

1049 search results - page 207 / 210
» Parallel Simulation for Aviation Applications
Sort
View
ICS
2003
Tsinghua U.
15 years 2 months ago
AEGIS: architecture for tamper-evident and tamper-resistant processing
We describe the architecture for a single-chip aegis processor which can be used to build computing systems secure against both physical and software attacks. Our architecture ass...
G. Edward Suh, Dwaine E. Clarke, Blaise Gassend, M...
INFOCOM
2002
IEEE
15 years 2 months ago
Towards Simple, High-performance Schedulers for High-aggregate Bandwidth Switches
— High-aggregate bandwidth switches are those whose port count multiplied by the operating line rate is very high; for example, a 30 port switch operating at 40 Gbps or a 1000 po...
Paolo Giaccone, Balaji Prabhakar, Devavrat Shah
GECCO
2010
Springer
191views Optimization» more  GECCO 2010»
15 years 2 months ago
Initialization parameter sweep in ATHENA: optimizing neural networks for detecting gene-gene interactions in the presence of sma
Recent advances in genotyping technology have led to the generation of an enormous quantity of genetic data. Traditional methods of statistical analysis have proved insufficient i...
Emily Rose Holzinger, Carrie C. Buchanan, Scott M....
INFOCOM
1998
IEEE
15 years 1 months ago
TCP Behavior of a Busy Internet Server: Analysis and Improvements
The rapid growth of the World Wide Web in recent years has caused a significant shift in the composition of Internet traffic. Although past work has studied the behavior of TCP dy...
Hari Balakrishnan, Venkata N. Padmanabhan, Sriniva...
ISCA
1994
IEEE
117views Hardware» more  ISCA 1994»
15 years 1 months ago
Evaluating Stream Buffers as a Secondary Cache Replacement
Today's commodity microprocessors require a low latency memory system to achieve high sustained performance. The conventional high-performance memory system provides fast dat...
Subbarao Palacharla, Richard E. Kessler