462 search results - page 55 / 93 » Parallel algorithm for hardware implementation of inverse ha... |
85
Voted
ISPASS
2009
IEEE
2009
IEEE
Machine learning based online performance prediction for runtime parallelization and task scheduling
15 years 4 months ago
—With the emerging many-core paradigm, parallel programming must extend beyond its traditional realm of scientific applications. Converting existing sequential applications as w...
SIGCOMM
2009
ACM
15 years 4 months ago
2009
ACM
The routing architecture of the original 4.4BSD [3] kernel has been deployed successfully without major design modification for over 15 years. In the unified routing architectur...
ISCAS
2003
IEEE
15 years 2 months ago
2003
IEEE
A new vision chip, SCAMP-2, has been developed in a 0.35µm CMOS technology. In this paper, the design of the chip is presented, with particular emphasis on its readout architectu...
ICCD
2006
IEEE
15 years 6 months ago
2006
IEEE
— A reduced complexity LDPC decoding method is presented that dramatically reduces wire interconnect complexity, which is a major issue in LDPC decoders. The proposed Split-Row m...
ISBI
2006
IEEE
15 years 3 months ago
2006
IEEE
This contribution describes a novel non-contact fluorescence optical tomography scheme which utilizes multiple area illumination patterns, to reduce the illposedness of the inver...