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SIPS
2008
IEEE
15 years 4 months ago
Unified decoder architecture for LDPC/turbo codes
Low-density parity-check (LDPC) codes on par with convolutional turbo codes (CTC) are two of the most powerful error correction codes known to perform very close to the Shannon li...
Yang Sun, Joseph R. Cavallaro
IPPS
2006
IEEE
15 years 3 months ago
Bio-sequence database scanning on a GPU
Protein sequences with unknown functionality are often compared to a set of known sequences to detect functional similarities. Efficient dynamic programming algorithms exist for t...
Weiguo Liu, Bertil Schmidt, Gerrit Voss, Adrian Sc...
101
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IEEEPACT
2002
IEEE
15 years 2 months ago
Using the Compiler to Improve Cache Replacement Decisions
Memory performance is increasingly determining microprocessor performance and technology trends are exacerbating this problem. Most architectures use set-associative caches with L...
Zhenlin Wang, Kathryn S. McKinley, Arnold L. Rosen...
ISLPED
2006
ACM
105views Hardware» more  ISLPED 2006»
15 years 3 months ago
Reducing power through compiler-directed barrier synchronization elimination
Interprocessor synchronization, while extremely important for ensuring execution correctness, can be very costly in terms of both power and performance overheads. Unfortunately, m...
Mahmut T. Kandemir, Seung Woo Son
ASAP
2005
IEEE
142views Hardware» more  ASAP 2005»
15 years 3 months ago
Decimal Floating-Point Square Root Using Newton-Raphson Iteration
With continued reductions in feature size, additional functionality may be added to future microprocessors to boost the performance of important application domains. Due to growth...
Liang-Kai Wang, Michael J. Schulte