Sciweavers

462 search results - page 68 / 93
» Parallel algorithm for hardware implementation of inverse ha...
Sort
View
83
Voted
IPPS
2009
IEEE
15 years 4 months ago
Energy minimization for periodic real-time tasks on heterogeneous processing units
Adopting multiple processing units to enhance the computing capability or reduce the power consumption has been widely accepted for designing modern computing systems. Such confi...
Jian-Jia Chen, Andreas Schranzhofer, Lothar Thiele
ARC
2006
Springer
124views Hardware» more  ARC 2006»
15 years 1 months ago
A Flexible Multi-port Caching Scheme for Reconfigurable Platforms
Abstract. Memory accesses contribute sunstantially to aggregate system delays. It is critical for designers to ensure that the memory subsystem is designed efficiently, and much wo...
Su-Shin Ang, George A. Constantinides, Peter Y. K....
PACT
2005
Springer
15 years 3 months ago
Optimal Behavior of a Moving Creature in the Cellular Automata Model
The goal of our investigation is to find automatically the best rule for a cell in the cellular automata model. The cells are either of type Obstacle, Empty or Creature. Only Crea...
Mathias Halbach, Rolf Hoffmann
74
Voted
DAC
2003
ACM
15 years 10 months ago
Compiler-generated communication for pipelined FPGA applications
In this paper, we describe a set of compiler analyses and an implementation that automatically map a sequential and un-annotated C program into a pipelined implementation, targete...
Heidi E. Ziegler, Mary W. Hall, Pedro C. Diniz
CODES
2005
IEEE
15 years 3 months ago
Novel architecture for loop acceleration: a case study
In this paper, we show a novel approach to accelerate loops by tightly coupling a coprocessor to an ASIP. Latency hiding is used to exploit the parallelism available in this archi...
Seng Lin Shee, Sri Parameswaran, Newton Cheung