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HOTI
2008
IEEE
15 years 4 months ago
High-Speed, Short-Latency Multipath Ethernet Transport for Interconnections
In this paper, we propose an Ethernet-based transmission-guaranteed, congestion-controlled network using a simplified multi-path aggregation scheme. Multi-path aggregation increas...
Nobuyuki Enomoto, Hideyuki Shimonishi, Junichi Hig...
CODES
2003
IEEE
15 years 2 months ago
Design space exploration of a hardware-software co-designed GF(2m) galois field processor for forward error correction and crypt
This paper describes a hardware-software co-design approach for flexible programmable Galois Field Processing for applications which require operations over GF(2m ), such as RS an...
Wei Ming Lim, Mohammed Benaissa
DATE
2007
IEEE
99views Hardware» more  DATE 2007»
15 years 4 months ago
A non-intrusive isolation approach for soft cores
Cost effective SOC test strongly hinges on parallel, independent test of SOC cores, which can only be ensured through proper core isolation techniques. While a core isolation mech...
Ozgur Sinanoglu, Tsvetomir Petrov
CAMP
2005
IEEE
15 years 3 months ago
Real-Time Low Level Feature Extraction for On-Board Robot Vision Systems
Abstract— Robot vision systems notoriously require large computing capabilities, rarely available on physical devices. Robots have limited embedded hardware, and almost all senso...
Roberto Pirrone, Giuseppe Careri, F. Saverio Fabia...
CAV
2008
Springer
131views Hardware» more  CAV 2008»
14 years 11 months ago
Validating High-Level Synthesis
The growing design-productivity gap has made designers shift toward using high-level languages like C, C++ and Java to do system-level design. High-Level Synthesis (HLS) is the pro...
Sudipta Kundu, Sorin Lerner, Rajesh Gupta