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ICS
2003
Tsinghua U.
15 years 2 months ago
Reducing register ports using delayed write-back queues and operand pre-fetch
In high-performance wide-issue microprocessors the access time, energy and area of the register file are often critical to overall performance. This is because these pararmeters g...
Nam Sung Kim, Trevor N. Mudge
ICS
2003
Tsinghua U.
15 years 2 months ago
AEGIS: architecture for tamper-evident and tamper-resistant processing
We describe the architecture for a single-chip aegis processor which can be used to build computing systems secure against both physical and software attacks. Our architecture ass...
G. Edward Suh, Dwaine E. Clarke, Blaise Gassend, M...
ICDCSW
2002
IEEE
15 years 2 months ago
Class-Based Delta-Encoding: A Scalable Scheme for Caching Dynamic Web Content
Abstract—Caching static HTTP traffic in proxy-caches has reduced bandwidth consumption and download latency. However, web-caching performance is hard to increase further due to ...
Konstantinos Psounis
ICPP
2002
IEEE
15 years 2 months ago
A Selection Technique for Replicated Multicast Video Servers
Abstract— In this paper, we propose a selection technique for replicated multicast video streams from different servers. We assume that there exist replicated video servers, each...
Akihito Hiromori, Hirozumi Yamaguchi, Keiichi Yasu...
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ICPP
2002
IEEE
15 years 2 months ago
Software Caching using Dynamic Binary Rewriting for Embedded Devices
A software cache implements instruction and data caching entirely in software. Dynamic binary rewriting offers a means to specialize the software cache miss checks at cache miss t...
Chad Huneycutt, Joshua B. Fryman, Kenneth M. Macke...
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