284 search results - page 11 / 57 » Parallel buffers for chip multiprocessors |
ASAP
2003
IEEE
15 years 2 months ago
2003
IEEE
On-chip implementation of multiprocessor systems requires the planarization of the interconnect network onto the silicon floorplan. Manual floorplanning approaches will become i...
HIPC
2003
Springer
15 years 2 months ago
2003
Springer
DAGSTUHL
2007
14 years 11 months ago
2007
Abstract. Two ways to exploit chips with a very large number of transistors are multicore processors and programmable logic chips. Some data parallel algorithms can be executed eï¬...
77
Voted
HPCA
2003
IEEE
15 years 10 months ago
2003
IEEE
Thread-level speculation provides architectural support to aggressively run hard-to-analyze code in parallel. As speculative tasks run concurrently, they generate unsafe or specul...
ISCA
2009
IEEE
15 years 4 months ago
2009
IEEE
With the shift towards chip multiprocessors (CMPs), exploiting and managing parallelism has become a central problem in computer systems. Many issues of parallelism management boi...