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» Parallel buffers for chip multiprocessors
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TPDS
2008
101views more  TPDS 2008»
14 years 9 months ago
An Energy-Oriented Evaluation of Buffer Cache Algorithms Using Parallel I/O Workloads
Power consumption is an important issue for cluster supercomputers as it directly affects running cost and cooling requirements. This paper investigates the memory energy efficienc...
Jianhui Yue, Yifeng Zhu, Zhao Cai
EUROPAR
2009
Springer
15 years 1 months ago
A Buffer Space Optimal Solution for Re-establishing the Packet Order in a MPSoC Network Processor
We consider a multi-processor system-on-chip destined for streaming applications. An application is composed of one input and one output queue and in-between, several levels of ide...
Daniela Genius, Alix Munier Kordon, Khouloud Zine ...
ISCA
2008
IEEE
148views Hardware» more  ISCA 2008»
15 years 4 months ago
Atomic Vector Operations on Chip Multiprocessors
The current trend is for processors to deliver dramatic improvements in parallel performance while only modestly improving serial performance. Parallel performance is harvested th...
Sanjeev Kumar, Daehyun Kim, Mikhail Smelyanskiy, Y...
ICPP
2003
IEEE
15 years 2 months ago
Performance and Power Impact of Issue-width in Chip-Multiprocessor Cores
In chip-multiprocessors (CMPs), the number of cores and the issue width of each core presents an important design trade-off to balance the amount of TLP and ILP between multi-thre...
Magnus Ekman, Per Stenström
ISCA
1998
IEEE
139views Hardware» more  ISCA 1998»
15 years 1 months ago
Simultaneous Multithreading: Maximizing On-Chip Parallelism
This paper examines simultaneous multithreading, a technique permitting several independent threads to issue instructions to a superscalar's multiple functional units in a si...
Dean M. Tullsen, Susan J. Eggers, Henry M. Levy