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» Parallel buffers for chip multiprocessors
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PPOPP
2009
ACM
15 years 10 months ago
A compiler-directed data prefetching scheme for chip multiprocessors
Data prefetching has been widely used in the past as a technique for hiding memory access latencies. However, data prefetching in multi-threaded applications running on chip multi...
Dhruva Chakrabarti, Mahmut T. Kandemir, Mustafa Ka...
ICS
1999
Tsinghua U.
15 years 1 months ago
Improving the performance of speculatively parallel applications on the Hydra CMP
Hydra is a chip multiprocessor (CMP) with integrated support for thread-level speculation. Thread-level speculation provides a way to parallelize sequential programs without the n...
Kunle Olukotun, Lance Hammond, Mark Willey
ISCA
2007
IEEE
208views Hardware» more  ISCA 2007»
15 years 3 months ago
Core fusion: accommodating software diversity in chip multiprocessors
This paper presents core fusion, a reconfigurable chip multiprocessor (CMP) architecture where groups of fundamentally independent cores can dynamically morph into a larger CPU, ...
Engin Ipek, Meyrem Kirman, Nevin Kirman, Jos&eacut...
IEEEPACT
2008
IEEE
15 years 4 months ago
Multitasking workload scheduling on flexible-core chip multiprocessors
While technology trends have ushered in the age of chip multiprocessors (CMP) and enabled designers to place an increasing number of cores on chip, a fundamental question is what ...
Divya Gulati, Changkyu Kim, Simha Sethumadhavan, S...
ISHPC
1999
Springer
15 years 1 months ago
Utilization of Cache Area in On-Chip Multiprocessor
On-chip multiprocessor can be an alternative to the wide-issue superscalar processor approach which is currently the mainstream to exploit the increasing number of transistors on ...
Hitoshi Oi, N. Ranganathan