Sciweavers

284 search results - page 23 / 57
» Parallel buffers for chip multiprocessors
Sort
View
ASPDAC
2005
ACM
133views Hardware» more  ASPDAC 2005»
14 years 11 months ago
A novel O(n) parallel banker's algorithm for System-on-a-Chip
This paper proposes a novel O(n) Parallel Banker’s Algorithm (PBA) with a best-case run-time of O(1), reduced from an ¢¤£¦¥¨§© run-time complexity of the original Ban...
Jaehwan John Lee, Vincent John Mooney III
USENIX
2001
14 years 11 months ago
Flexible Control of Parallelism in a Multiprocessor PC Router
SMP Click is a software router that provides both flexibility and high performance on stock multiprocessor PC hardware. It achieves high performance using device, buffer, and queu...
Benjie Chen, Robert Morris
ISCA
1994
IEEE
104views Hardware» more  ISCA 1994»
15 years 1 months ago
Exploring the Design Space for a Shared-Cache Multiprocessor
In the near future, semiconductor technology will allow the integration of multiple processors on a chip or multichipmodule (MCM). In this paper we investigate the architecture an...
Basem A. Nayfeh, Kunle Olukotun
92
Voted
VLSID
2001
IEEE
164views VLSI» more  VLSID 2001»
15 years 10 months ago
An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...
Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das
HPCC
2005
Springer
15 years 3 months ago
Factory: An Object-Oriented Parallel Programming Substrate for Deep Multiprocessors
Abstract. Recent advances in processor technology such as Simultaneous Multithreading (SMT) and Chip Multiprocessing (CMP) enable parallel processing on a single die. These process...
Scott Schneider, Christos D. Antonopoulos, Dimitri...