284 search results - page 26 / 57 » Parallel buffers for chip multiprocessors |
ASPDAC
2009
ACM
15 years 4 months ago
2009
ACM
— Multiprocessors on a chip are the reality of these days. Semiconductor industry has recognized this approach as the most efficient in order to exploit chip resources, but the ...
92
Voted
SBCCI
2009
ACM
15 years 4 months ago
2009
ACM
We present an application-driven customization methodology for energy-efficient inter-core communication in embedded multiprocessors. The methodology leverages configurable cach...
IPPS
2000
IEEE
15 years 2 months ago
2000
IEEE
The newly introduced Microprocessor Architecture for Java Computing MAJC supports parallelism in a hierarchy of levels: multiprocessors on chip,vertical micro threading, instruct...
TC
2008
14 years 9 months ago
2008
To support dynamic address translation in today's microprocessors, the first-level cache is accessed in parallel with a translation lookaside buffer (TLB). However, this curre...
95
Voted
RTSS
2007
IEEE
15 years 4 months ago
2007
IEEE
In the last years, a progressive migration from single processor chips to multi-core computing devices has taken place in the general-purpose and embedded system market. The devel...