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» Parallel buffers for chip multiprocessors
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IEEEPACT
2002
IEEE
15 years 2 months ago
Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power
Energy efficiency in microarchitectures has become a necessity. Significant dynamic energy savings can be realized for adaptive storage structures such as caches, issue queues, ...
Steve Dropsho, Alper Buyuktosunoglu, Rajeev Balasu...
IPPS
2003
IEEE
15 years 2 months ago
Parallel Direct Solution of Linear Equations on FPGA-Based Machines
The efficient solution of large systems of linear equations represented by sparse matrices appears in many tasks. LU factorization followed by backward and forward substitutions i...
Xiaofang Wang, Sotirios G. Ziavras
DEBS
2009
ACM
15 years 4 months ago
Parallel event processing for content-based publish/subscribe systems
Event processing systems are a promising technology for enterprise-scale applications. However, achieving scalability yet maintaining high performance is a challenging problem. Th...
Amer Farroukh, Elias Ferzli, Naweed Tajuddin, Hans...
CSC
2010
14 years 7 months ago
An Evaluation of Parallel Knapsack Algorithms on Multicore Architectures
Emergence of chip multiprocessor systems has dramatically increased the performance potential of computer systems. Since the amount of exploited parallelism is directly influenced ...
Hammad Rashid, Clara Novoa, Apan Qasem
69
Voted
DAC
2009
ACM
15 years 4 months ago
PiCAP: a parallel and incremental capacitance extraction considering stochastic process variation
It is unknown how to include stochastic process variation into fast-multipole-method (FMM) for a full chip capacitance extraction. This paper presents a parallel FMM extraction us...
Fang Gong, Hao Yu, Lei He