284 search results - page 31 / 57 » Parallel buffers for chip multiprocessors |
IPPS
2006
IEEE
15 years 3 months ago
2006
IEEE
This paper presents a helper thread prefetching scheme that is designed to work on loosely-coupled processors, such as in a standard chip multi-processor (CMP) system and in an in...
VLSID
2007
IEEE
15 years 10 months ago
2007
IEEE
Today, VLSI systems for computationally demanding applications are being built as Systems-on-Chip (SoCs) with a distributed memory sub-system which is shared by a large number of ...
75
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DATE
2006
IEEE
15 years 3 months ago
2006
IEEE
NoC architectures can be adopted to support general communications among multiple IPs over multi-processor Systems on Chip (SoCs). In this work we illustrate the modeling and simu...
83
Voted
HPCA
2009
IEEE
15 years 10 months ago
2009
IEEE
Driven by continuing scaling of Moore's law, chip multiprocessors and systems-on-a-chip are expected to grow the core count from dozens today to hundreds in the near future. ...
110
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ISCA
2002
IEEE
15 years 2 months ago
2002
IEEE
We develop an availability solution, called SafetyNet, that uses a unified, lightweight checkpoint/recovery mechanism to support multiple long-latency fault detection schemes. At...