284 search results - page 33 / 57 » Parallel buffers for chip multiprocessors |
154
Voted
ASPLOS
2009
ACM
15 years 10 months ago
2009
ACM
While deterministic replay of parallel programs is a powerful technique, current proposals have shortcomings. Specifically, software-based replay systems have high overheads on mu...
80
Voted
ISCA
2000
IEEE
15 years 2 months ago
2000
IEEE
The microprocessor industry is currently struggling with higher development costs and longer design times that arise from exceedingly complex processors that are pushing the limit...
IPPS
2003
IEEE
15 years 2 months ago
2003
IEEE
With the current trend in integration of more complex systems on chip there is a need for better communication infrastructure on chip that will increase the available bandwidth an...
109
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HOTI
2011
IEEE
13 years 9 months ago
2011
IEEE
Abstract—Network-on-Chips (NoCs) paradigm is fast becoming a defacto standard for designing communication infrastructure for multicores with the dual goals of reducing power cons...
MASCOTS
2007
2007
A Novel Flow Control Scheme for Best Effort Traffic in NoC Based on Source Rate Utility Maximization
14 years 11 months ago
—Advances in semiconductor technology, has enabled designers to put complex, massively parallel multiprocessor systems on a single chip. Network on Chip (NoC) that supports high ...