284 search results - page 39 / 57 » Parallel buffers for chip multiprocessors |
ICCD
2007
IEEE
15 years 6 months ago
2007
IEEE
As chip multiprocessors (CMPs) become the only viable way to scale up and utilize the abundant transistors made available in current microprocessors, the design of on-chip network...
102
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3DIC
2009
IEEE
15 years 29 days ago
2009
IEEE
Abstract— Networks-on-chip (NoC) is emerging as a key onchip communication architecture for multiprocessor systemson-chip (MPSoC). In traditional electronic NoCs, high bandwidth ...
101
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HPCA
2007
IEEE
15 years 10 months ago
2007
IEEE
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On t...
ICPP
2009
IEEE
15 years 4 months ago
2009
IEEE
—Lattice Boltzmann Methods (LBM) are used for the computational simulation of Newtonian fluid dynamics. LBM-based simulations are readily parallelizable; they have been implemen...
APPT
2007
Springer
15 years 3 months ago
2007
Springer
It is a great challenge to map network processing tasks to processing resources of advanced network processors, which are heterogeneous and multi-threading multiprocessor System-on...