284 search results - page 40 / 57 » Parallel buffers for chip multiprocessors |
SPAA
2005
ACM
15 years 3 months ago
2005
ACM
This paper shows for the first time that elimination, a scaling technique formerly applied only to counters and LIFO structures, can be applied to FIFO data structures, specific...
HPCA
1996
IEEE
15 years 1 months ago
1996
IEEE
The current multiprocessors such asCray T3D support interprocessor communication using partitioned dimension-order routers (PDRs). In a PDR implementation, the routing logic and sw...
116
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FPL
2006
Springer
15 years 1 months ago
2006
Springer
With current FPGAs, designers can now instantiate several embedded processors, memory units, and a wide variety of IP blocks to build a single-chip, high-performance multiprocesso...
96
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IEEEHPCS
2010
14 years 7 months ago
2010
Stream languages explicitly describe fork-join parallelism and pipelines, offering a powerful programming model for many-core Multi-Processor Systems on Chip (MPSoC). In an embedd...
HPCA
2003
IEEE
15 years 10 months ago
2003
IEEE
Java-based middleware, and application servers in particular, are rapidly gaining importance as a new class of workload for commercial multiprocessor servers. SPEC has recognized ...