284 search results - page 43 / 57 » Parallel buffers for chip multiprocessors |
145
click to vote
ASAP
2011
IEEE
2011
IEEE
High-throughput Contention-Free concurrent interleaver architecture for multi-standard turbo decoder
13 years 9 months ago
—To meet the higher data rate requirement of emerging wireless communication technology, numerous parallel turbo decoder architectures have been developed. However, the interleav...
ISLPED
2006
ACM
15 years 3 months ago
2006
ACM
Interprocessor synchronization, while extremely important for ensuring execution correctness, can be very costly in terms of both power and performance overheads. Unfortunately, m...
ISCA
2000
IEEE
15 years 2 months ago
2000
IEEE
While architects understandhow to build cost-effective parallel machines across a wide spectrum of machine sizes (ranging from within a single chip to large-scale servers), the re...
67
Voted
IEEEPACT
2007
IEEE
15 years 3 months ago
2007
IEEE
Under current worst-case design practices, manufacturers specify conservative values for processor frequencies in order to guarantee correctness. To recover some of the lost perfo...
SAC
2009
ACM
15 years 4 months ago
2009
ACM
The prediction of the correct secondary structures of large RNAs is one of the unsolved challenges of computational molecular biology. Among the major obstacles is the fact that a...