284 search results - page 46 / 57 » Parallel buffers for chip multiprocessors |
66
Voted
MICRO
2007
IEEE
15 years 3 months ago
2007
IEEE
Modern chip multiprocessors (CMPs) are designed to exploit both instruction-level parallelism (ILP) within processors and thread-level parallelism (TLP) within and across processo...
IPPS
2006
IEEE
15 years 3 months ago
2006
IEEE
Due to shared cache contentions and interconnect delays, data prefetching is more critical in alleviating penalties from increasing memory latencies and demands on Chip-Multiproce...
IEEEPACT
2005
IEEE
15 years 3 months ago
2005
IEEE
In this paper we compare the performance of area equivalent small, medium, and large-scale multithreaded chip multiprocessors (CMTs) using throughput-oriented applications. We use...
79
Voted
ICS
2005
Tsinghua U.
15 years 3 months ago
2005
Tsinghua U.
We propose an organization for the on-chip memory system of a chip multiprocessor, in which 16 processors share a 16MB pool of 256 L2 cache banks. The L2 cache is organized as a n...
80
Voted
DAGSTUHL
2006
14 years 11 months ago
2006
Current and future communications systems have to provide a large degree of flexibility e.g. to provide multi-service ability, seamless roaming, softinfrastructure upgrading, user-...