284 search results - page 57 / 57 » Parallel buffers for chip multiprocessors |
IEEEPACT
2008
IEEE
15 years 4 months ago
2008
IEEE
Communication overheads are one of the fundamental challenges in a multiprocessor system. As the number of processors on a chip increases, communication overheads and the distribu...
101
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IEEEPACT
2006
IEEE
15 years 3 months ago
2006
IEEE
As chip multiprocessors (CMPs) become increasingly mainstream, architects have likewise become more interested in how best to share a cache hierarchy among multiple simultaneous t...
183
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GLVLSI
2011
IEEE
14 years 1 months ago
2011
IEEE
This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...
118
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IEEEPACT
2005
IEEE
15 years 3 months ago
2005
IEEE
Current integration trends embrace the prosperity of single-chip multi-core processors. Although multi-core processors deliver significantly improved system throughput, single-thr...