284 search results - page 5 / 57 » Parallel buffers for chip multiprocessors |
IPPS
2000
IEEE
15 years 2 months ago
2000
IEEE
Abstract. Computer vision is a challenging data intensive application. Currently, superscalar architectures dominate the processor marketplace. As more transistors become available...
ICCD
2005
IEEE
15 years 6 months ago
2005
IEEE
In this paper, we present and evaluate three temperature-sensitive loop parallelization strategies for array-intensive applications executed on chip multiprocessors in order to re...
CAL
2006
14 years 9 months ago
2006
This paper evaluates asymmetric cluster chip multiprocessor (ACCMP) architectures as a mechanism to achieve the highest performance for a given power budget. ACCMPs execute serial ...
SIGARCH
2008
14 years 9 months ago
2008
This paper presents a parallelization framework for emerging applications on the future chip multiprocessors (CMPs). With the continuing prevalence of CMP and the number of on-die...
HPCA
2006
IEEE
15 years 10 months ago
2006
IEEE
Previous proposals for power-aware thread-level parallelism on chip multiprocessors (CMPs) mostly focus on multiprogrammed workloads. Nonetheless, parallel computation of a single...