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AAAI
2008
15 years 6 months ago
CIGAR: Concurrent and Interleaving Goal and Activity Recognition
In artificial intelligence and pervasive computing research, inferring users' high-level goals from activity sequences is an important task. A major challenge in goal recogni...
Derek Hao Hu, Qiang Yang
GLVLSI
2011
IEEE
344views VLSI» more  GLVLSI 2011»
14 years 8 months ago
Circuit design of a dual-versioning L1 data cache for optimistic concurrency
This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...
Azam Seyedi, Adrià Armejach, Adrián ...
LCTRTS
2010
Springer
15 years 2 months ago
Translating concurrent action oriented specifications to synchronous guarded actions
Concurrent Action-Oriented Specifications (CAOS) model the behavior of a synchronous hardware circuit as asynchronous guarded at an abstraction level higher than the Register Tran...
Jens Brandt, Klaus Schneider, Sandeep K. Shukla
EMSOFT
2006
Springer
15 years 8 months ago
Scheduling-independent threads and exceptions in SHIM
Concurrent programming languages should be a good fit for embedded systems because they match the intrinsic parallelism of their architectures and environments. Unfortunately, typ...
Olivier Tardieu, Stephen A. Edwards
HPCA
2006
IEEE
16 years 4 months ago
Reducing resource redundancy for concurrent error detection techniques in high performance microprocessors
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
Sumeet Kumar, Aneesh Aggarwal