This paper describes a tiling technique that can be used by application programmers and optimizing compilers to obtain I/O-efficient versions of regular scientific loop nests. Du...
Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanuja...
A cache line size has a signi cant e ect on missrate and memorytra c. Today's computers use a xed line size, typically 32B, which may not be optimalfor a given application. O...
Alexander V. Veidenbaum, Weiyu Tang, Rajesh K. Gup...
Java supports heterogeneous applications by transforming a heterogeneous network of machines into a homogeneous network of Java virtual machines. This abstracts over many of the c...
Gul Agha, Mark Astley, Jamil A. Sheikh, Carlos A. ...
Abstract. In this paper, we present a methodology for mapping an Embedded Signal Processing ESP application onto HPC platforms such that the throughput performance is maximized. Pr...
We study the relationship between the number of rounds needed to repeatedly perform a private computation i.e., where there are many sets of inputs sequentially given to the play...
Eyal Kushilevitz, Rafail Ostrovsky, Adi Rosé...