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135
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ICIP
2009
IEEE
16 years 4 months ago
Architecture Design Of A High-performance Dual-symbol Binary Arithmetic Coder For Jpeg2000
The embedded-block coding with optimized truncation (EBCOT), which consists of a bit-plane coder (BPC) and a binary arithmetic coder (BAC), is the bottleneck in realizing a high-p...
113
Voted
ICCAD
2004
IEEE
124views Hardware» more  ICCAD 2004»
16 years 7 days ago
Architectural-level synthesis of digital microfluidics-based biochips
Microfluidics-based biochips offer a promising platform for massively parallel DNA analysis, automated drug discovery, and real-time biomolecular recognition. Current techniques f...
Fei Su, Krishnendu Chakrabarty
DATE
2009
IEEE
98views Hardware» more  DATE 2009»
15 years 10 months ago
A real-time application design methodology for MPSoCs
This paper presents a novel technique for the modeling, simulation, and analysis of real-time applications on MultiProcessor Systems-on-Chip (MPSoCs). This technique is based on a...
Giovanni Beltrame, Luca Fossati, Donatella Sciuto
ICC
2009
IEEE
279views Communications» more  ICC 2009»
15 years 10 months ago
Non-Regenerative Multicarrier MIMO Relay Communications Based on Minimization of Mean-Squared Error
Abstract—In this paper we propose non-regenerative multicarrier multiple-input multiple-output (MIMO) relay techniques that minimize the mean-squared error (MSE) of the signal wa...
Yue Rong
CCGRID
2008
IEEE
15 years 9 months ago
Joint Communication and Computation Task Scheduling in Grids
In this paper we present a multicost algorithm for the joint time scheduling of the communication and computation resources that will be used by a task. The proposed algorithm sel...
Kostas Christodoulopoulos, Nikolaos D. Doulamis, E...