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» Parallel error correcting codes
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94
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CORR
2007
Springer
146views Education» more  CORR 2007»
15 years 17 days ago
Coding for Errors and Erasures in Random Network Coding
Abstract—The problem of error-control in random linear network coding is considered. A “noncoherent” or “channel oblivious” model is assumed where neither transmitter nor...
Ralf Koetter, Frank R. Kschischang
100
Voted
ISCC
2000
IEEE
15 years 5 months ago
Light Weight Security for Parallel Access to Multiple Mirror Sites
Mirror sites approach has been proposed recently for reducing the access delay and providing load balancing in network servers. In the mirror site approach a file, such as a multi...
Bülent Yener
VTS
2007
IEEE
203views Hardware» more  VTS 2007»
15 years 6 months ago
Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code
Conventional error correcting code (ECC) schemes used in memories and caches cannot correct double bit errors caused by a single event upset (SEU). As memory density increases, mu...
Avijit Dutta, Nur A. Touba
84
Voted
CORR
2007
Springer
113views Education» more  CORR 2007»
15 years 17 days ago
Can Punctured Rate-1/2 Turbo Codes Achieve a Lower Error Floor than their Rate-1/3 Parent Codes?
— In this paper we concentrate on rate-1/3 systematic parallel concatenated convolutional codes and their rate-1/2 punctured child codes. Assuming maximum-likelihood decoding ove...
Ioannis Chatzigeorgiou, Miguel R. D. Rodrigues, Ia...
85
Voted
GLOBECOM
2006
IEEE
15 years 6 months ago
Cyclic Codes Tailored to a Known Set of Error Patterns
— We propose a high-rate error-pattern control code based on a generator polynomial targeting a specific set of known dominant error patterns. This code is based on first const...
Jihoon Park, Jaekyun Moon