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» Parallel error correcting codes
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DATE
2010
IEEE
162views Hardware» more  DATE 2010»
15 years 7 months ago
Error resilience of intra-die and inter-die communication with 3D spidergon STNoC
: Scaling down in very deep submicron (VDSM) technologies increases the delay, power consumption of on-chip interconnects, while the reliability and yield decrease. In high perform...
Vladimir Pasca, Lorena Anghel, Claudia Rusu, Ricca...
TCOM
2008
63views more  TCOM 2008»
15 years 2 months ago
A general construction of constrained parity-check codes for optical recording
This paper proposes a general and systematic code design method to efficiently combine constrained codes with parity-check (PC) codes for optical recording. The proposed constraine...
Kui Cai, Kees A. Schouhamer Immink
DFG
2009
Springer
15 years 9 months ago
Interactive Communication, Diagnosis and Error Control in Networks
s of the work of our research group are given in the following poster of the final meeting. Network Coding Network Coding has emerged as a new paradigm that has influenced Inform...
Rudolf Ahlswede, Harout K. Aydinian
AAECC
2007
Springer
113views Algorithms» more  AAECC 2007»
15 years 8 months ago
Generalized Sudan's List Decoding for Order Domain Codes
Abstract. We generalize Sudan’s list decoding algorithm without multiplicity to evaluation codes coming from arbitrary order domains. The number of correctable errors by the prop...
Olav Geil, Ryutaroh Matsumoto
INFOCOM
2000
IEEE
15 years 6 months ago
Adaptive Two-Level Unequal Error Protection Convolutional Code Scheme for Wireless ATM Networks
Abstract—Because the wireless asynchronous transfer mode (ATM) networks are often constrained with the limited link bandwidth and error prone characteristics, forward error corre...
Zhenqiang Sun, Shigetomo Kimura, Yoshihiko Ebihara