Sciweavers

831 search results - page 77 / 167
» Parallel error correcting codes
Sort
View
CODES
2003
IEEE
15 years 10 months ago
A fast parallel reed-solomon decoder on a reconfigurable architecture
This paper presents a software implementation of a very fast parallel Reed-Solomon decoder on the second generation of MorphoSys reconfigurable computation platform, which is targ...
Arezou Koohi, Nader Bagherzadeh, Chengzi Pan
APPROX
2005
Springer
96views Algorithms» more  APPROX 2005»
15 years 10 months ago
Tolerant Locally Testable Codes
An error-correcting code is said to be locally testable if it has an efficient spot-checking procedure that can distinguish codewords from strings that are far from every codeword...
Venkatesan Guruswami, Atri Rudra
DAC
1997
ACM
15 years 8 months ago
A Parallel/Serial Trade-Off Methodology for Look-Up Table Based Decoders
A methodology for architecture exploration of look-up table based decoders is presented. For the degree of parallel processing a trade-off can be made by exploring system level an...
Claus Schneider
APCCAS
2006
IEEE
251views Hardware» more  APCCAS 2006»
15 years 10 months ago
Design of a Dynamic PCM Selector for Non-deterministic Environment
—The quality of transmission is very important in digital communication. However, in non-deterministic environment or different transmission message signal, bit error rate of PCM...
Liang-Bi Chen, Ing-Jer Huang, Yuan-Long Jeang
MICRO
2003
IEEE
152views Hardware» more  MICRO 2003»
15 years 10 months ago
A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor
Single-event upsets from particle strikes have become a key challenge in microprocessor design. Techniques to deal with these transient faults exist, but come at a cost. Designers...
Shubhendu S. Mukherjee, Christopher T. Weaver, Joe...