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IJPP
2011
99views more  IJPP 2011»
14 years 4 months ago
Regular Lattice and Small-World Spin Model Simulations Using CUDA and GPUs
Data-parallel accelerator devices such as Graphical Processing Units (GPUs) are providing dramatic performance improvements over even multicore CPUs for lattice-oriented applicatio...
Kenneth A. Hawick, Arno Leist, Daniel P. Playne
86
Voted
ICS
2005
Tsinghua U.
15 years 3 months ago
A heterogeneously segmented cache architecture for a packet forwarding engine
As network traffic continues to increase and with the requirement to process packets at line rates, high performance routers need to forward millions of packets every second. Eve...
Kaushik Rajan, Ramaswamy Govindarajan
IPPS
2009
IEEE
15 years 4 months ago
Implementing and evaluating multithreaded triad census algorithms on the Cray XMT
Commonly represented as directed graphs, social networks depict relationships and behaviors among social entities such as people, groups, and organizations. Social network analysi...
George Chin Jr., Andrès Márquez, Sut...
74
Voted
DAC
2003
ACM
15 years 10 months ago
Compiler-generated communication for pipelined FPGA applications
In this paper, we describe a set of compiler analyses and an implementation that automatically map a sequential and un-annotated C program into a pipelined implementation, targete...
Heidi E. Ziegler, Mary W. Hall, Pedro C. Diniz
IWOMP
2007
Springer
15 years 3 months ago
Support for Fine Grained Dependent Tasks in OpenMP
OpenMP is widely used for shared memory parallel programming and is especially useful for the parallelisation of loops. When it comes to task parallelism, however, OpenMP is less p...
Oliver Sinnen, Jsun Pe, Alexander Vladimirovich Ko...